Delta sigma modulation transforms an analog input signal into a digital like pulse width modulated two-state bit stream that can be transmitted more reliably through a noisy communication channel. A delta-sigma pulse width modulator includes an integrator that integrates the difference between an input signal and a feedback signal. The feedback signal is proportional to the output of the modulator, which in turn is the result of the comparison between periodic waveform, typically a triangle or saw-tooth waveform, and the integrator output. Thus, a continuous time varying, analog, input signal is converted to a pulse width modulated digital signal. At the receiving side, a synchronous demodulator reconstructs the envelope of the transmitted signal.
FIG. 1 is an illustrative circuit diagram representing a known delta sigma PWM modulator circuit 100. The illustrative example delta sigma modulator circuit (the “modulator”) 100 includes an integrator circuit 102 including an integrating capacitor 103, a comparator circuit 104, a one-bit digital-to-analog converter (“DAC”) circuit 106 and a periodic clock signal generator circuit 108 coupled as shown. The example integrator 102 includes an operational amplifier circuit 110 that includes external first input node 114 coupled to receive an analog input signal, a second node 114 coupled to receive a reference signal, and an integrator output node 116. In some embodiments, the first input node 112 is coupled to an inverted input of the amplifier 110 and the second node 114 is coupled to a non-inverted input of the amplifier 110. The integrator includes the integrator capacitor (Cint) 103 coupled between the integrator output node 116 and the first input node 112. A resistance R is coupled to the first input node 112 to act as a trans-conductance to covert an external analog input voltage signal to an analog input current signal. The first input node 112 is coupled to summing node 118 whereat an analog input current signal and a feedback signal are summed together. Changes in the value of the sum occur with time varying changes in the analog input signal and corresponding changes in the feedback signal result in charging and discharging of the integrating capacitor (Cint) 103. During normal operation, the example integrator 102 produces a time varying integrator output voltage that is proportional to the integral of the difference between the external input analog signal and the feedback signal.
The example comparator circuit 104 includes first input node 120 coupled to be responsive to an output voltage signal provided by the integrator circuit 102 and includes a second input node 122 coupled to be responsive to a periodic reference voltage signal produced by the periodic clock waveform generator circuit 108. In some embodiments, the periodic clock signal waveform generator circuit 108 produces a periodic triangle wave voltage signal. Alternatively, in some embodiments the periodic clock signal generator circuit 108 produces a different signal shape having a ramp component such as a saw-tooth wave voltage signal. In some embodiments, the first and second input nodes 120, 122, of the comparator circuit 104 are coupled to its inverting and non-inverting inputs, respectively. The comparator 104 produces a continuous time output signal at a comparator output node 124 that is indicative of the integrator output signal. The comparator output signal is provided as a feedback input to the one-bit DAC circuit 106.
The example one-bit DAC 106 includes switch circuitry 126 responsive to the comparator output signal that selectively couples the integrator's input node to either an Iref source 128 reference current or to an Iref sink 130 reference current to thereby convert the comparator output voltage signal to a comparator feedback current signal. More particularly, in response to the comparator output signal, which also acts as the modulator output voltage signal, the DAC's switch circuitry 126 couples a selected one or the other of the Iref source 128 and the Iref sink 130 to the integrator's input node 112, so as to generate a square wave current signal at the integrator input node whose average value for every PWM period is proportional to the PWM modulator output voltage. FIG. 2 is an illustrative block diagram representing certain details of an example known periodic clock waveform signal generator circuit 108 used in some embodiments of the modulator of FIG. 1. The example periodic clock waveform generator circuit 106 includes an oscillator circuit 132 that produces a periodic square wave having frequency FC that is used to produce a PWM triangle waveform whose period is 1/FC. The periodic clock signal generator 108 includes an IPWM current source 134 and an IPWM current sink 136 and a capacitor (Cosc) 138. Switch circuitry 140 is configured to alternately couple the IPWM source 134 and the IPWM sink 136 to the capacitor (Cosc) 138 in response to the periodic square wave so as to alternately charge and discharge the (Cosc) 138. The alternate charging and discharging of the (Cosc) 138 produces a triangle waveform that is provided at a reference node of the example comparator of some embodiments of the modulator of FIG. 1.